//Insert declarations of global clocks, variables, constants and channels.
const N 2;
const wireCount0 2;
int[0, wireCount0] bus0Wire;
const wireCount1 4;
int[0, wireCount1] bus1Wire;
chan begSig, endSig, begBuff, endBuff, begMem,endMem;
chan switch, tick, tack;
int space[N*2];
int reg[N];
int[0,1] ready[N];
int[0,N] openBus;
int[0,3] turn;
int starting:=0;
urgent chan start;
//clock systemtime;
Adderchan begA, endA;
chan begAp, endAp;
chan begS, endS;
chan begSp, endSpStartWaitArbiterconst period;
chan beg, endconst unsafe 15625;
const refreshTime 100;
const maxSafe unsafe-25;
clock memtimer, timer;StartReadyTransferRefreshFinishSetupRegisterconst startId, idMem, idBuff, spaceId, status; int bus;
chan begBuff, endBuff;
chan begMem, endMemWaitReadyStartTransferMTransferBPreparebufferBusy1bufferBusy2Prepare2bufferBusy3inBufferconst startId, id, size, initial, regId, inWire, outWire; int inBus, outBus;
chan begPut; chan endPut; const putAmount;
chan begGet; chan endGet; const getAmountIdleWritingReadingReadingWritingStartWritingIgnoreReadIgnoreReadoutBufferconst startId, id, size, initial, regId, inWire, outWire; int inBus, outBus;
chan begPut; chan endPut; const putAmount;
chan begGet; chan endGet; const getAmountIdleWritingReadingReadingWritingStartReadingIgnoreWriteIgnoreWriteTimerconst startId, period, countclock time;PrepareTickingPauseStartTackingBusconst startId, me, wireCount, skipCount;
int bus;
chan beg, endint counter;BeginEndWaitStartStopFinishBeginFinishEndSkipTackWaitForTickSkipTickStarterStartStayArbiterTconst startId, me;
chan beg, endconst unsafe 3072; // 3125;
const refreshCycle 20;
int counter;
//3119 prepare for refresh
const maxSafe unsafe-6;
//3125+20=3139 end of full refresh
const maxUnsafe unsafe+refreshCycle;
StartReadyTransferWaitSettingSetupFinishSetupSwitchSkipTack2SwitchingSkipTackWaitForTickSkipTickSetting2WaitForTick2SkipTick2FinishSwitchSwitching2SwithRefreshRefreshLeaveRefreshArbiterNTconst startId, me;
chan beg, endStartReadyTransferWaitSettingSetupFinishSetupSwitchSkipTack2SwitchingSkipTackWaitForTickSkipTickSetting2WaitForTick2SkipTick2FinishSwitchSwitching2ArbiterTOconst startId, me;
chan beg, endconst unsafe 15625/5; //3125;
const refreshCycle 20;
int counter;
//3119 prepare for refresh
const maxSafe unsafe-6;
//3125+20=3139 end of full refresh
const maxUnsafe unsafe+refreshCycle;
StartReadyTransferWaitSettingSetupFinishSetupSwitchSkipTack2SwitchingSkipTackWaitForTickSkipTickSetting2WaitForTick2SwitchRefreshRefreshSkipTack1//Insert process assignments.
starter:=Starter();
//Timer: const startId, period, count
timer:=Timer(7, 5, 3);
//Bus: const startId, me, wireCount, skipCount;int bus; chan beg, end
bus0:=Bus(1, 0, wireCount0, 1, bus0Wire, begSig, endSig);
bus1:=Bus(4, 1, wireCount1, 1, bus1Wire, begBuff, endBuff);
//InBuff: const startId, id, size, initial, regId, inWire, outWire; int inBus, outBus;
//chan begPut; chan endPut; const putAmount;
//chan begGet; chan endGet; const getAmount
buf0:=inBuffer(2, 0, 8*512, 0, 0, 0, 1, bus0Wire, bus1Wire, begSig, endSig, 8, begBuff, endBuff, 32);
//OutBuff: const startId, id, size, initial, regId, inWire, outWire; int inBus, outBus;
//chan begPut; chan endPut; const putAmount;
//chan begGet; chan endGet; const getAmount
buf1:=outBuffer(3, 1, 8*512, 8*512, 1, 3, 1, bus1Wire, bus0Wire, begBuff, endBuff, 32, begSig, endSig, 16);
//Register: const startId, idMem, idBuff, spaceId, status; int bus;
//chan begBuff, endBuff, begMem, endMem
reg0:=Register(5, 0, 0, 0, 0, bus1Wire, begBuff, endBuff, begMem, endMem);
reg1:=Register(6, 1, 2, 1+N, 512, bus1Wire, begBuff, endBuff, begMem, endMem);
//ArbiterNT: const startId, me; chan beg, end
//arbiter:=ArbiterNT(0, 2, begMem, endMem);
arbiter:=ArbiterTO(0, 2, begMem, endMem);
//Edit system definition.
system starter, timer, bus0, bus1, buf0, buf1, reg0, reg1, arbiter;