//Insert declarations of global clocks, variables, constants and channels.
const N 9;
const wireCount0 9;
int[0, wireCount0] bus0Wire;
const wireCount1 18;
int[0, wireCount1] bus1Wire;
chan begSig, endSig, begBuff, endBuff, begMem,endMem;
chan switch;
int space[N*2];
int reg[N];
int[0,1] ready[N];
int[0,N] openBus;
chan tick, tack;
int[0,3] turn;
int starting:=0;
urgent chan start;
//clock systemtime;
BusOLDconst wireCount, delay, period;
int bus;
chan beg, endclock timer;
BeginEndWaitStartBufferconst startId, id, size, inWire, outWire; int inBus, outBus;
chan begPut; chan endPut; const putAmount;
chan begGet; chan endGet; const getAmountIdleWritingReadingReadingWritingOverflowStartAdderchan begA, endA;
chan begAp, endAp;
chan begS, endS;
chan begSp, endSpSwitchCycleCycleRegisterconst startId, idMem, idBuff, spaceId, status; int bus;
chan begBuff, endBuff;
chan begMem, endMemWaitReadyStartTransferMTransferBPreparebufferBusy1bufferBusy2Prepare2bufferBusy3Arbiterconst period;
chan beg, endconst unsafe 15625;
const refreshTime 100;
const maxSafe unsafe-25;
clock memtimer, timer;StartReadyTransferRefreshFinishSetupinBufferconst startId, id, size, initial, regId, inWire, outWire; int inBus, outBus;
chan begPut; chan endPut; const putAmount;
chan begGet; chan endGet; const getAmountIdleWritingReadingReadingWritingStartWritingIgnoreReadIgnoreReadoutBufferconst startId, id, size, initial, regId, inWire, outWire; int inBus, outBus;
chan begPut; chan endPut; const putAmount;
chan begGet; chan endGet; const getAmountIdleWritingReadingReadingWritingStartReadingIgnoreWriteIgnoreWriteArbiterSconst period;
chan beg, endconst unsafe 625;
const refreshTime 100;
const maxSafe unsafe-25;
clock memtimer, timer;StartReadyTransferRefreshFinishSetupArbiterNconst period;
chan beg, endclock timer;StartReadyTransferFinishSetupTimerconst startId, period, countclock time;PrepareTickingPauseStartTackingArbiterNTconst startId, me;
chan beg, endStartReadyTransferWaitSettingSetupFinishSetupSwitchSkipTack2SwitchingSkipTackWaitForTickSkipTickSetting2WaitForTick2SkipTick2FinishSwitchSwitching2Busconst startId, me, wireCount, skipCount;
int bus;
chan beg, endint counter;BeginEndWaitStartStopFinishBeginFinishEndSkipTackWaitForTickSkipTickStarterStartStayArbiterTconst startId, me;
chan beg, endconst unsafe 2304; // 3125;
const refreshCycle 20;
int counter;
//3119 prepare for refresh
const maxSafe unsafe-6;
//3125+20=3139 end of full refresh
const maxUnsafe unsafe+refreshCycle;
StartReadyTransferWaitSettingSetupFinishSetupSwitchSkipTack2SwitchingSkipTackWaitForTickSkipTickSetting2WaitForTick2SkipTick2FinishSwitchSwitching2SwithRefreshRefreshLeaveRefreshArbiterTOconst startId, me;
chan beg, endconst unsafe 3124; //2304;
const refreshCycle 20;
int counter;
//3119 prepare for refresh
const maxSafe unsafe-6;
//3125+20=3139 end of full refresh
const maxUnsafe unsafe+refreshCycle;
StartReadyTransferWaitSettingSetupFinishSetupSwitchSkipTack2SwitchingSkipTackWaitForTickSkipTickSetting2WaitForTick2SwitchRefreshRefreshSkipTack1//Insert process assignments.
starter:=Starter();
//Timer: const period, count
timer:=Timer(21, 5, 3);
//BusOLD: const wireCount, delay, period; int bus; chan beg, end
// bus0:=BusOLD(wireCount0, 20, 10, bus0Wire, begSig, endSig);
//Bus: const me, wireCount, skipCount; int bus; chan beg, end
bus0:=Bus(1, 0, wireCount0, 1, bus0Wire, begSig, endSig);
// const id, size, initial, regId, inWire, outWire; int inBus, outBus;
// chan begPut; chan endPut; const putAmount;
// chan begGet; chan endGet; const getAmount
buf0:=inBuffer(2, 0, 1024, 0, 0, 0, 1, bus0Wire, bus1Wire,
begSig, endSig, 8, begBuff, endBuff, 32);
buf1:=inBuffer(3, 1, 1024, 0, 1, 1, 3, bus0Wire, bus1Wire,
begSig, endSig, 8, begBuff, endBuff, 32);
buf2:=outBuffer(4, 2, 512, 512, 2, 5, 2, bus1Wire, bus0Wire,
begBuff, endBuff, 32, begSig, endSig, 8);
buf3:=outBuffer(5, 3, 2048, 1024, 3, 7, 3, bus1Wire, bus0Wire,
begBuff, endBuff, 32, begSig, endSig, 16);
buf4:=outBuffer(6, 4, 512, 512, 4, 9, 4, bus1Wire, bus0Wire,
begBuff, endBuff, 32, begSig, endSig, 8);
buf5:=outBuffer(7, 5, 512, 512, 5, 11, 5, bus1Wire, bus0Wire,
begBuff, endBuff, 32, begSig, endSig, 8);
buf6:=outBuffer(8, 6, 2048, 1024, 6, 13, 6, bus1Wire, bus0Wire,
begBuff, endBuff, 32, begSig, endSig, 16);
buf7:=inBuffer(9, 7, 2048, 0, 7, 7, 15, bus0Wire, bus1Wire,
begSig, endSig, 16, begBuff, endBuff, 32);
buf8:=inBuffer(10, 8, 2048, 0, 8, 8, 17, bus0Wire, bus1Wire,
begSig, endSig, 16, begBuff, endBuff, 32);
bus1:=Bus(11, 1, wireCount1, 1, bus1Wire, begBuff, endBuff);
// const idMem, idBuff, spaceId, status; chan begBuff, endBuff; chan begMem, endMem
reg0:=Register(12, 0, 0, 0, 0, bus1Wire, begBuff, endBuff, begMem, endMem);
reg1:=Register(13, 1, 2, 1, 0, bus1Wire, begBuff, endBuff, begMem, endMem);
reg2:=Register(14, 2, 4, 2+N, 512, bus1Wire, begBuff, endBuff, begMem, endMem);
reg3:=Register(15, 3, 6, 3+N, 512, bus1Wire, begBuff, endBuff, begMem, endMem);
reg4:=Register(16, 4, 8, 4+N, 512, bus1Wire, begBuff, endBuff, begMem, endMem);
reg5:=Register(17, 5, 10, 5+N, 512, bus1Wire, begBuff, endBuff, begMem, endMem);
reg6:=Register(18, 6, 12, 6+N, 512, bus1Wire, begBuff, endBuff, begMem, endMem);
reg7:=Register(19, 7, 14, 7, 0, bus1Wire, begBuff, endBuff, begMem, endMem);
reg8:=Register(20, 8, 16, 8, 0, bus1Wire, begBuff, endBuff, begMem, endMem);
//ArbiterN: const period; chan beg, end
//arbiter:=ArbiterN(5, begMem, endMem);
//ArbiterNT: const const me; chan beg, end
arbiter:=ArbiterTO(0, 2, begMem, endMem);
//Edit system definition.
system starter, timer, bus0, bus1,
buf0, buf1, buf2, buf3, buf4, buf5, buf6, buf7, buf8,
reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8,
arbiter;