Computer & Network Architectures

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Schedule

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The schedule is preliminary and can be changed.

Lecture 1: Introduction, Fundamentals of Digital Logic, Data and Program Representation

[Alexandre] Abstract: After an introduction on computer architectures I will present basics of digital circuits at the transistor level, building up to gates and integrated circuits. If time permits, I will start on how numbers are represented in binary.

Reading: [Comer] Chapter 1, Chapter 2, and Chapter 3.

Slides: Introduction, Digital Circuits, Data Representation.

Lecture 2: Data and Program Representation (cont.), Processor Types

[Alexandre] Abstract: I will finish on number representation and start on processor architectures and types. You will see the different execution units of processors, what registers are used for, and the type of instructions available on processors.

Reading: [Comer] Chapter 3, Chapter 4, and Chapter 5.
Extra reading for keen students.
Wikipedia page on binary numbers (for counting in binary) and wikipedia page on bitwise operations.

Slides: Data Representation, Variety of processors.

Exercises: Suggested exercises [Comer] 3.1, 3.2, 3.3, or 3.5. Also you may try these (except 2 since there is no Sparc available). Try 1.5 and 3 that are important. Solution for one of these exercises (don't cheat) is here.

Lecture 3: Instruction Sets and Representation

[Alexandre] Abstract: I present the different processor types, in particular CISC and RISC, and the different associated instruction sets. I briefly treat of pipelines.

Reading: [Comer] Chapter 5.
[Comer] Self-read chapter 18.

Slides: Processor Types and Instruction Sets.

Exercises: Same as last time.

Lecture 4: Microcode, Assembly Languages

[Alexandre] Abstract: I will finish on instruction representation, focusing on operands this time. I will present assembly languages and take some examples from IA32/64 processors.
Note: For those of you who are unfamiliar with bitwise operators please look at newly added links to Wikipedia for lecture 2 and re-read lecture 1 where logical gates with truth tables were presented.

Reading: [Comer] Chapter 6, Chapter 7, and Chapter 8.
Download and browse Intel instruction set references (2A/2B) to see for yourself what the real stuff looks like.

Slides: Operand Encoding, Assembly Languages, Microcode.

Exercises: You should try one exercise from the book and one question on code analysis. The exercise can be done at different depths depending on your interest. We will split these exercises on two exercise sessions and I will complete them for keen students.

• Exercises 4.1, 4.2, and 4.3.
• Study this wikipedia page on GAS. Alternatively you can try the next exercise and use the page to check out answers to your questions.
• Download this test program. Log on the system (homer, marge, or lisa), use your own Linux box to compile it, or use the Debian image provided for VirtualBox. Try some of these different compilations:
  • gcc -o test_program0 test_program.c -O0 -Wall
  • gcc -o test_program1 test_program.c -O1 -Wall
  • gcc -o test_program2 test_program.c -O2 -Wall
  • gcc -o test_program3 test_program.c -O3 -Wall
• Disassemble the programs with the command objdump -dC test_program. Observe the structure, identify the calls, find the test function, look at the differences.
• Use the instruction manuals (Intel) to find out what the compiler did with the original program. Important note: The ordering of the operands used by the gnu tool is following a different convention than Intel's manuals. You need to invert the order to understand them, e.g., instead of using destination,source the tool uses source,destination. In addition, assembly instructions are suffixed by 'q', 'l', 'w', or 'b'. This suffix specifies the size of the operand (quad:64, long:32, word:16, byte:8). Do this on one program, not all of them. I told you enough during the last lecture for you to manage.
• If you use the application servers: The machines on the application servers run a 64-bit OS and you will obtain 64-bit binaries. Compile with the -m32 option to obtain 32-bit binaries. Examine the new code (by disassembling it).
• Unfortunately it is not possible to get kdbg on the application servers but it is installed on your VirtualBox image (alternatively you can install it on your Linux box). Recompile with the -g option (for debugging). Then run the debugger with, e.g., kdbg test_program2. Executing step by step at the C level is not very interesting. Click on the '+' to see the assembly. Execute step-by-step at the assembly level and observe the registers (open the view registers window). To make the execution more interesting, you can comment the loop and execute the function with hand-picked values, e.g., 0x11111111.
• For keen students (advanced) you can study this wikipedia page too. The interesting sections are the ones on patterns.

Lecture 5: Physical and Virtual Memories

[Alexandre] Abstract: I will present the hardware support for virtual memory. This part complements PSS. I have mentioned caches enough in the course so you can self-read that part and it is better to get some experience to really understand its effect - see exercises for next time.

Reading: [Comer] Chapters 9, 10, and 11.
Self-reading: [Comer] Chapter 14 - only mentioned in the lecture.

Slides: Virtual and Physical Memories.

Exercises: Continue on the exercises from last time. You can also try the following advanced exercise on inline assembly in C.

• Download this dummy addition program and study this page to understand how the inline asm works with gcc. Prefer the notation used in the example with symbolic names in bracket rather than the explicit %number notation that is more error prone.
• Generate the assembly with gcc -Wall -O3 -S add1_ex.c. Look at how registers were allocated by the compiler and how the asm code fits into the rest of the program. You can compile with gcc -Wall -O3 -o add1_ex add1_ex.c if you want an executable.
• Download this bit test program. Look at what the bit test function does and replace its body by a simpler asm equivalent (use bsf to find the bit, mov to store -1, and look for a suitable jump instruction). To do a relative jump without messing up the labels, use numbers and jump either forward (f) or backward (b). Example: jmp 1f to jump to label 1: forward, or jmp 1b if the label is placed backward (relative to the jmp instruction). Check the assembly generated by the compiler and the register allocation.
• You can also try to download this double add program that treats 2 ints like one large int. This is an artificial example because here the type long long would do this (in 32 bits). Anyway, implement the function that adds the low integers and the high integers, taking the carry into account (use add and adc). Check the assembly generated by the compiler and the register allocation.

Solutions: (Don't look at them before trying the exercises, don't cheat) bit test and double addition programs.

Lecture 6: Introduction to Computer Networks, The Internet, The OSI Protocol Layers

[Alexandre] Abstract: I will introduce computer networks, what packet switching is, and the different layer of the OSI protocol stack.

Reading: [Comer] Chapter 12 and the photocopies for the exercise.
[KuroseRoss] Chapter 1.

Slides: Chapter 1 ppt / pdf.

Exercises:

• Read the photocopies you have on the memory mountain and download memperf from its homepage. Experiment with it and produce the memory mountain of your computer.
• Experiment with the different matrix multiplication variants given in the photocopies. You can use this program to experiment with that if you wish. It has a few empty placeholders to be filled with different variants that you can try. The program generates a matrix, inverts it, and mutiplies it by its inverse (and check it is identity as a test for your multiplication).

Lecture 7: Application Layer I

[Alexandre] Abstract: I will start on the application layer (OSI), treating client-servers, and a few protocols (http, ftp, smtp, pop).

Reading: [KuroseRoss] Chapter 2.

Slides: Chapter 2 pdf / pptx.

Exercises 4th/5th edition: Exercises R1/R2, R2/R1, R3/R4, R9/R10, R11/R12, R12/R11, R14, R19/R18, R23/R25, and R25/R24. Problems P1/P4, P2/P1, P5, P18/P23, P24 (fig. 1.28(b) in 5th edition is wrong), P26/P25.

Solutions: here (restricted access from AAU).

Lecture 8: Application Layer II

[Alexandre] Abstract: I will finish on the application layer, treating DNS, bittorrent, and socket programming.

Reading: [KuroseRoss] Chapter 2.

Slides: Application layer.

Exercises 4th/5th edition: Try traceroute and telnet. Exercises R1/R2, R3/R1, R7/R6, R8, R9/R15, and R15/R17. Problems P1, P2/P5, P7/P8, and P12/P11.

Solutions: here (restricted access from AAU).

Lecture 9: Transport Layer I

[Arne] Abstract: I will start on the transport layer (OSI), treating multiplexing, demultiplexing, and udp.

Reading: [KuroseRoss] Chapter 3.

Slides: Transport layer.

Exercises 4th/5th edition Exercises R18, R22/R24, R24/R26, and R28. Problems P16, P20, P23/P21, and P25/P24

Solutions: here (restricted access from AAU).

Lecture 10: Transport Layer II

[Arne] Abstract: I will finish on the transport layer, treating tcp and congestion.

Reading: [KuroseRoss] Chapter 3.

Slides: Transport layer.

Exercises: Exercises R1/R2, R2/R3, R3/R4, R8/R5, R12/R12, R13/R13, P3/P2, P9/P9, P21/P22

Solutions: here (restricted access from AAU).

Lecture 11: Network Layer I

[Arne] Abstract: I will start on the network layer (OSI), treating datagram networks, routing, ip, dhcp, and nat.

Reading: [KuroseRoss] Chapter 4.

Slides: Network layer.

Exercises 4th/5th edition (Chapter 3): R14/R16, R16/R15, R17/R17, R18/R18, P17/P17, P25/P26, P30/P34, P38/P37

Solutions: here (restricted access from AAU).

Lecture 12: Network Layer II

[Arne] Abstract: I will finish on the network layer (OSI), treating tunneling, routing algorithms, and multicast routing.

Reading: [KuroseRoss] Chapter 4.

Slides: Network layer.

Exercises 4th/5th edition (Chapter 4): R2/R3, R6/R6, R9/R7, R11/R10, R20/R20, R18/R19, P1/P1, P8/P8, P11/P10, P15/P16, P19/P18

Solutions: here (restricted access from AAU).

Lecture 13: Link Layer I

[Arne] Abstract: I will start on the link layer and LANs, treating error detection and correction, and multiple access control.

Reading: [KuroseRoss] Chapter 5.

Slides: Link layer.

Exercises 4th/5th edition (Chapter 4): R21/R22, R23/R23, R22/R21, R24/R25, R25/R29, R28/R30, P20/P21, P22/P25, P23/P27, P24/P23, P28/P28

Solutions: here (restricted access from AAU).

Lecture 14: Link Layer II

[Arne] Abstract: I will finish on the link layer and LANs, treating MAC, ARP, PPP, ATM, and virtual networks.

Reading: [KuroseRoss] Chapter 5.

Slides: Link layer, and various.

Exercises 4th/5th edition (Chapter 5): R2/R2, R1/R1, R9/R9, R10/R7, R11/R13, P4/P4, P11/P9, P12/P19, P14/P12, P15/P17

Solutions: here (restricted access from AAU).

Lecture 15: Wireless and Mobile Networks

[Arne] Abstract: I will treat wireless networks, in particular 802.11 and 802.15, and mobile ip. Also, I will give a summary of network security concepts.

Reading: [KuroseRoss] Chapter 6 and Chapter 8.

Slides: Wireless networks and Network security.

Exercises 4th/5th edition (Chapter 5): R13/R12, R12/R11, R14/R14, P20/P21, P24/P23, P25/P28, P27/P24

Solutions: here (restricted access from AAU).

Exercises 4th/5th edition (Chapter 6): R3/R4, R5/R6, R7/R8, R12/R13, R9/R14, R18/R18, P6/P5, P5/P7, P7/P6. To be solved May 3, 8:15 - 10:00.

Exercises 4th/5th edition (Chapter 8): R1/R2, R6/R3, R9/R5, R16/R6, R3/R7, R17/R8, R18/R10, R12/R13, R13/R14. To be solved May 3, 8:15 - 10:00.

Solutions: here (restricted access from AAU).